Device Sizing Techniques for High Yield Minimum-Energy Subthreshold Circuits
نویسندگان
چکیده
Subthreshold CMOS logic can be used to provide energyefficient computation in scenarios where performance is not a critical concern. Analysis in existing literature, and explored in this work, demonstrates that the use of minimum-sized devices can offer the greatest energy-efficiency, but in the face of variation, upsizing schemes must be considered to reduce gate failure rates. We explore the impact of variation on low-voltage functionality of gates and propose a novel methodology for determining the gate failure rates under different sizing schemes. We show that optimal sizing for min energy is dependent on loading.
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